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This brief presents an evaluation tool of the noise figure reduction that can be achieved by adding a low-noise amplifier in a near- $f_{\max}$ frequency receiver. After choosing a suitable topology and assessing its frequency dependence, an analytical derivation is carried out and preliminary frequency constraints are found. The analytical assessment is followed by a practical example using the...
This paper presents three single balanced down-converting mixer designs in CMOS 65 nm technology. The three designs operate at 95 GHz and reach a maximum conversion gain of 8, 6.9 and 10.2 dB respectively. Due to the use of single balanced topology, the designs occupy a relatively small core area of 0.89×0.51, 0.078×0.14 and 0.053×0.17 mm2 and their DC power consumption is only 26, 29 and 12.4 mW.
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