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This paper presents three single balanced down-converting mixer designs in CMOS 65 nm technology. The three designs operate at 95 GHz and reach a maximum conversion gain of 8, 6.9 and 10.2 dB respectively. Due to the use of single balanced topology, the designs occupy a relatively small core area of 0.89×0.51, 0.078×0.14 and 0.053×0.17 mm2 and their DC power consumption is only 26, 29 and 12.4 mW.
This paper describes circuit design and measurement results of a multi-tanh bipolar rms power detector (PD) for applications in E band (65–86 GHz) frequency range. The PD is designed and fabricated in IBM 0.13um SiGe technology. In the matched frequency range, the measured input dynamic range is over 40 dB, withstanding an input power of 17dBm, with an overall sensitivity of 27.5 mV/dB. The output...
In this paper, we explore the use of multi-band radio frequency interconnect (or RF-I) with signal propagation at the speed of light to provide shortcuts in a many core network-on-chip (NoC) mesh topology. We investigate the costs associated with this technology, and examine the latency and bandwidth benefits that it can provide. Assuming a 400 mm2 die, we demonstrate that in exchange for 0.13% of...
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