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We apply several low power technologies to save both total energy and peak power consumption for video codec VLSI designs. Our technologies include two-layer clock gating, utilization of skip mode, memory hierarchy with memory access units, and internal memory partitioning. We implement a standby mode to reduce both clock power and memory power for saving total energy. We also use a novel technology,...
We propose a very high-throughput fully hardwired CABAC encoder for ultra-high resolution video. Our architecture includes hardwired circuits for binarization, context modeling, neighbor data access, and a six-stage pipelined binary arithmetic encoder (BAE). Our BAE can encode multiple bins per cycle. In order to keep up with the BAE throughput, we propose acceleration methods for the bin and context...
For all video applications, large amounts of data are processed within a bounded time. These data are usually stored in a low-cost slow external DRAM which results in high memory bandwidth requirement. The memory bandwidth will dominate the system performance, especially for applications running on embedded systems. In this paper, we propose an effective dictionary-based compression and de-compression...
We present a high-performance and low-power pure-hardware accelerator for decoding H.264/AVC video. We propose novel VLSI architectures for every stage of the decoding pipeline. We wrap the decoder core with an AMBA bus interface, integrate it into a multimedia SOC platform, and verify it with FPGA prototyping. In order to reduce external memory traffic, we propose a memory fetch unit to increase...
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