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Three-dimensional (3D) on-chip memory stacking has been proposed as a promising solution to the “memory wall” challenge with the benefits of low access latency, high data bandwidth, and low power consumption. The stacked memory tiers leverage through-silicon-vias (TSVs) to communicate with logic tiers, and thus dramatically reduce the access latency and improve the data bandwidth without the constraint...
To address the “memory wall” challenge, on-chip memory stacking has been proposed as a promising solution. The stacking memory adopts three-dimensional (3D) IC technology, which leverages through-silicon-vias (TSVs) to connect layers, to dramatically reduce the access latency and improve the bandwidth without the constraint of I/O pins. To demonstrate the feasibility of 3D memory stacking, this paper...
We propose a very high-throughput fully hardwired CABAC encoder for ultra-high resolution video. Our architecture includes hardwired circuits for binarization, context modeling, neighbor data access, and a six-stage pipelined binary arithmetic encoder (BAE). Our BAE can encode multiple bins per cycle. In order to keep up with the BAE throughput, we propose acceleration methods for the bin and context...
We present a high-performance and low-power pure-hardware accelerator for decoding H.264/AVC video. We propose novel VLSI architectures for every stage of the decoding pipeline. We wrap the decoder core with an AMBA bus interface, integrate it into a multimedia SOC platform, and verify it with FPGA prototyping. In order to reduce external memory traffic, we propose a memory fetch unit to increase...
In this paper, a high throughput fully hardwired CABAC encoder is proposed for real-time encoding video of ultra high resolution, e.g., QFHD (3840times2160). We analyze the distribution of bins in various syntax elements and accordingly propose a new architecture which includes an optimized context memory access scheme, a multi-bin binary arithmetic encoder (BAE), and an SE-specific cycle-reduction...
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