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Multiple-reference-frame, quarter-pixel accuracy, and variable-block-size motion estimation (VBSME) employed in H.264/AVC is one of the major contributors to its outstanding compression efficiency and video quality. However, due to its high computational complexity, VBSME needs acceleration for real-time application. We propose a high throughput hardware architecture for H.264/AVC fractional motion...
We present a high-performance hardware architecture for H.264/AVC full-mode intra-frame encoding. We propose a novel method to alleviate performance bottleneck caused by the long data dependency loop among 4times4 blocks. Synthesized into a TSMC 0.13 mum CMOS cell library, our design takes 212 K gates to run at 138 MHz and is able to real-time encode 1080HD (1920times1088) video sequences at 30 frames...
We propose a near optimal hardware architecture for deblocking filter in H.264/MPEG-4 AVC. We propose a novel filtering order and a data reuse strategy that result in significant saving in filtering time, local memory usage, and memory traffic. Every 16-16 macroblock requires 192 filtering operations. After a few initialization cycles, our 5-stage pipelined architecture is able to perform one filtering...
We propose an efficient hardware architecture for the Blowfish algorithm. The speed is up to 4 bit/clock, which is 9 times faster than a Pentium. By applying operator-rescheduling method, the critical path delay is improved by 21.7%. We have successfully implemented it using Compass cell library targeted at a 0.6 /spl mu/m TSMC SPTM CMOS process. The die size is 5.7/spl times/6.1 mm/sup 2/ and the...
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