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We propose a low-overhead method for delay fault testing in high-speed asynchronous pipelines. The key features of our work are: (i) testing strategies can be administered using low-speed testing equipment; (ii) testing is minimally-intrusive, i.e. very little testing hardware needs to be added; (iii) testing methods are extended to pipelines with forks and joins, which is an important first step...
We discuss a transistor-level test methodology for C2MOS asynchronous pipelines. Unlike their static CMOS counterparts, wherein testing for stuck-at faults and compliance to a few timing constraints typically suffices, dynamic asynchronous pipelines present new challenges which require more elaborate test solutions. More specifically, many gate-level input/output stuck-at faults of a static pipeline...
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