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We have found that fully silicided (FUSI) gate is a promising technology for the first time not only for breaking the gate stack scaling limitation on low standby power (LSTP) devices but for keeping continuous scaling of high density SRAM (HDSRAM) for 45nm node and beyond. It is shown that FUSI will drastically suppress the fluctuation of threshold voltage (Vth) of fine transistors of HDSRAM. We...
We developed a less layout-dependent epitaxially grown SiGe (eSiGe) source/drain (S/D) technique for pFET. We found that the effective stressor region of eSiGe existed only near the channel and that the volume effect of eSiGe was small. On the basis of this mechanism, a new recess RIE and a new epitaxial growth technology were developed, so that the gate-pitch dependence, S/D length dependence and...
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