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At the 90-nm, leakage currents bring standby power to an unacceptable level and circuit level techniques become mandatory. However applying these techniques must be robust and practical. In this paper we focus not only on leakage reduction solutions but also on their deployment as a worldwide infrastructure as the added-value resides not only in the techniques themselves but also in the way they are...
The new generation of multimedia-application processors requires a drastic leakage reduction to bring the standby current to 50/spl mu/A. An efficient set of leakage reduction techniques, including power gating, memory retention, voltage scaling, and dual V/sub t/, is employed on a 50M transistor, 80mm/sup 2/ IC, fabricated in a 90nm CMOS technology, resulting in a 40/spl times/ leakage reduction.
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