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As the development of processors/SoCs (System-on-Chips), NoC (Network-on-Chip) consumes an increasing fraction of the modern processors/SoCs power. Thus, designing energy-efficient NoC architecture is imperative. Multi-NoC (Multiple Network-on-Chip) behaves well in power gating for reducing leakage power, which constitutes a significant fraction of NoC power. In this paper, we propose CRA, a novel...
As the core count grows rapidly, NoC (Network-on-Chip) consumes an increasing fraction of the modern processors/SoCs (System-on-Chips) power. It is thus very important to design energy-efficient NoC architecture. Multi-NoC (Multiple Network-on-Chip) has demonstrated its advantages in power gating for reducing leakage power, which constitutes a significant fraction of NoC power. In this paper, we propose...
With the development of multiple processors SoC (system on chip), there are more and more challenges to the design of NoC (network-on-chip), one of which is to design energy-efficient NoC architecture, due to its large power consumption. Multi-NoC (multiple network-on-chip) has been proposed to save leakage power for its advantages in power gating network components. In this paper, we propose a hybrid...
Multi-NoC (multiple network-on-chip) has demonstrated its advantages in power gating for reducing leakage power. This work presents Chameleon, a novel heterogeneous Multi-NoC design. Chameleon employs a fine-grained power gating algorithm which exploits power saving opportunities at different levels of granularity simultaneously. Integrated with a performance-aware traffic allocation policy, Chameleon...
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