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A WR1.5 frequency multiplier circuit using standard CMOS 65nm technology is presented. Careful choice of device and its gate size leads to fair amount of output power compared to other expensive high performance semiconductor process. Accumulation-mode varactor device is chosen for its high non-linearity and gate size of the varactor is enlarged until self-resonance occur at fundamental frequency...
Layered Division Multiplexing (LDM) is a novel non-orthogonal multiplexing access (NOMA) technique, based on power allocation techniques, which has been recently included in the ATSC 3.0 Digital Television Terrestrial (DTT) standard. In the recent literature, the LDM capabilities have been studied just for the two layered case, mainly when one of the layers is targeting mobile/indoor services and...
This paper presents a new microfabrication method for surface ion traps and experimental results with trapped ions. Fabricating ion trap chips is a very formidable task because the top electrodes are vertically spaced more than 10 µm from the bottom electrodes with an indented dielectric layer in the middle. Previous ion traps were fabricated using TEOS timed etch or tungsten sacrificial etch techniques...
This paper presents a novel channel sounding system based on MIMO software defined radio architecture. It was developed for the evaluation of the beyond 4 G mobile communication systems operating at 11 GHz in which the multi-link MIMO technology will be adopted. 4Ô4 MIMO channel sounder was developed as the first prototype, and the advantages and issues are discussed based on the several performance...
A 300 GHz amplifier is fabricated using indium-phosphide (InP) double-heterojunction bipolar transistor (DHBT) technology. The cascade chain in the amplifier contains six unit cells each containing a pair of common-base DHBTs in differential configuration. A total of three signal lines run through to the unit-cell to obtain the differential-mode amplifier gain and provide proper dc bias. Measured...
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