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Operating up to 5.5 GHz with 1-mW power consumption, a 90-nm CMOS programmable frequency divider with eight stages of new static D-flip-flop-based (2/1) divider cells is presented, where the supply voltage of 1.0 V is employed. The divider achieves a full modulus range from 1 to 256 and operates over a wide range maintaining up to 4 GHz with 30-dBm input power. The divider also accomplishes a power...
This paper describes and resolves the false locking issue in phase-locked loops (PLLs) with π-phase detector. In order to verify the proposed approach for acquisition and capture range performances of π-phase detector, the phase-controlled-current-source (PCCS) using the reversing scheme is implemented in TSMC 0.18μm 1P6M CMOS technology. In the simulation results, the locking time of the proposed...
This paper presents a novel 2/3 divider cell circuit design for a truly modular programmable frequency divider with high-speed, low-power, and high input-sensitivity features. In this paper, the proposed flip-flop based 2/3 divider cell adopts dynamic E-TSPC circuit that not only reduces power consumption, but also improves operation speed and input sensitivity. The whole design was implemented using...
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