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This letter provides channel-stress behavior results induced by a local strain technique which consists of the process combination of a damascene-gate and top-cut tensile stress SiN liner for narrow channel-width nFETs using 3-D stress simulations and demonstrations. The dummy-gate removal, which is an intrinsic step in the damascene-gate process, is found to enhance tensile channel stress along the...
Mobility and velocity enhancements of hole on Si (110) and (100) substrates are accurately investigated for short-channel highly-strained pFETs. Local channel stress in short gate length is successfully observed for damascene gate pFETs with stressors by UV-Raman spectroscopy. A high channel stress of -2.4 GPa is measured for a 30-nm gate length device. Hole mobility and saturation velocity are precisely...
Dynamical programming processes in electrically programmable (writable) fuses (e-fuses) with a narrow link of p-doped Ni-silicided poly-Si or Cu were studied, through slow I-V measurements of an e-fuse and a blowing FET made separately. The two I-V curves depicted in the same graph gave valuable knowledge of programming processes and suitable programming conditions. Maps of final resistance values...
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