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Technological solutions for the transfer to large area microstrip radiation silicon sensors are presented for the upgrade of the ATLAS detector. A new Automatic Layout Generation Tool has been developed to easily adapt the design of the sensors, investigating also the fabrication processes involved in 6-inch wafer technology. Inter-strip and radiation hardness characterization of prototype sensors...
The optimization of resurfed LDMOS transistors is considered in this paper. A new interdigitated LDMOS layout, characterized by a waved gate electrode, which theoretically predicts an improvement around 10% in the device specific ON-resistance, RONxS, iS presented. The experimental results from devices fabricated on epi-wafers with optimal properties, obtained from an analytical model for the device...
A distributed modellization of the specific ON-resistance is experimentally corroborated for VDMOS transistors with different cellular designs. The results for low voltage capability devices show differences for the optinmum percentage of the cell area outside the body at which the minimum of the specific ON-resistance occurs and for this minimum value compared with previous formulations. In addition,...
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