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Demands for the low power VLSI have been pushing the aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose Adaptive Supply Voltage Carry-Select Adder (CSA) based on the input vector patterns. A proposed level converter based on the Complementary Pass Transistor Logic (CPL) cancels out the delay penalty of level conversion. We achieved 26%...
This paper presents a low voltage differential current switch logic (LVDCSL) gate capable of achieving high performance for large fan-in gates. High fan-in is enabled by using a large height predischarged N-channel metal-oxide-semiconductor (NMOS) trees. The power penalty of an increased number of internal nodes in the gate is mitigated by restricting their voltage swings. The salient features of...
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