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We propose a Current Mirror Evaluation Logic (CMEL) and show (for 0.13µm technology) that this new logic achieves 28-to-47% (10-to-27%) delay reduction against high fan-in single/multi-stage domino (conditional keeper domino [1]) OR gates at an affordable power and area penalty. In addition, CMEL shows 54-to-95% (18-to- 45%) delay reduction against high fan-in single stage (multi-stage) domino AND...
We present a leakage tolerant dynamic circuit called Source Following Evaluation Gate (SFEG) which has high DC noise margin. Simulation results in 0.13µm and 0.1µm CMOS process technologies [1] show considerable degradation in noise immunity of domino circuits with threshold voltage scaling and/or increase of fan-in. Comparison with standard domino circuits indicates the noise immunity of 16-input...
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