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The extended scalability of Twin Flash memory cells down to 32nm half pitch is demonstrated in a conventional planar cell layout. Starting with 63nm line space array and doubling the number of word lines, a cell size of 0.0112μm 2 can be achieved. By dividing available space into 43nm cell width and 20nm space between adjacent cells the electrical cell characteristics could be maintained the...
We report on a new nanoelectronic planar three-terminal device, fabricated from III/V semiconductor-based heterosystems. Utilizing the benefits of selfgating and in-plane gates, the tunable three-terminal device presented exhibits strong non-linear input- and transfer-characteristics, both, at liquid Helium and at room temperature. For a given side-gate voltage, the devices input characteristics closely...
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