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This paper presents an embedded SRAM design for write buffer applications in flash memories. The write buffer is implemented with a newly proposed self-adaptive timing control circuit, an area-saving sense-latch circuit and 6 T SRAM cell units. A 2 kb SRAM macro with the area of 135 μm × 180 μm is implemented in and applied to a 128 Mb NOR flash memory with the SMIC 65 nm NOR flash memory process...
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