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This paper presents a DC/AC compact model for double-gate (DG) tunnel field-effect transistors (TFET) which is based on a unified analytical modeling framework. The closed-form model shows a good agreement with both, TCAD simulations and measurements on test structures. A Verilog-A implementation allows for a quick performance evaluation of the DC performance of logic cells. Results of a complementary...
In this paper a static noise margin (SNM) analysis is done for an 8T SRAM cell build up with complementary tunnel-FETs (TFETs). The simulations are done with the help of a Verilog-A implemented 2D DC compact model for a double-gate (DG) TFET, published in [1]. The compact model is adapted to measurement data of fabricated nanowire (NW) GAA TFETs before analyzing the hold/read and write SNM of the...
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