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This paper addresses the issue of delivering power to high performance 3D stacks such as a processor on cache stack. Through Silicon Vias (TSVs) with their associated keep out zones (KOZ) occupy only a small fraction of the die (
Through Silicon Vias (TSV) is a key enabler for interposer and 3Di technologies. As the TSV process integration is maturing, reliability is a key parameter to be studied. One such reliability wear-out mechanisms is electro-migration (EM). In this paper, we report on experimental electromigration studies of TSVs used in 3-Dimensional integration (3Di). While TSV themselves can carry large currents,...
300mm Si wafer-scale oxide fusion bonding and mechanical/wet etch assisted wafer thinning processes were combined with a TSV-last 3D integration strategy to fabricate electrical open/short yield learning on through-wafer electrical TSV test chains.
Differential thermal expansion mismatch between Cu and Si along with high aspect ratios required for TSV pose unique challenges to the integration and reliability of Cu TSV. A TSV structure that successfully mitigates these concerns has been integrated into CMOS with high K/metal gates. Data from test structures demonstrate no ‘Cu pumping’ or other deleterious effects to neighboring devices or interconnects...
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