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An ultra-thinning down to 2.6-um using 300-mm 2Gb DRAM wafer has been developed. Effects of Si thickness and Cu contamination at wafer backside in terms of DRAM yield and retention characteristics are described. Total thickness variation (TTV) after thinning was below 1.9-um within 300-mm wafer. A degradation of retention characteristics occurred after thinning down to 2.6-um while no degradation...
An ultra-thinning down to 4-µm using 300-mm wafer proven by 40-nm Node 2Gb DRAM has been developed for the first time. Three different types of thinning process including coarse grinding, fine grinding, and stress relief were optimized and an atomic level vacancy less than 10-nm in depth at backside of wafer was formed successively. Thickness uniformity even after thinning down to 4-µm was approximately...
The multi-stack processes for wafer-on-wafer (WOW) have been developed. The key features are bumpless interconnects adapted to TSVs and extendibility for chip-on-wafer (COW) taking high throughput into account. In order to realize the multi-stacked wafers with ultra thinned wafer of less than 10μm with an adhesive polymer, several processes have been optimized. The thickness of the wafer after back-grinding...
The multi-stack process on wafer-on-wafer (WOW) has been developed. In order to realize the multi-stacked wafer with ultra thinned wafer of less than 10 μm with adhesive polymer, several processes have been optimized. The wafer thickness after back-grinding was controlled within the total thickness variation (TTV) of 1.2 μm on wafer-level of 8 inch. For the side wall of though silicon vias (TSV),...
With evaluation of various dense silicon-oxy-nitride (SiON) films, a critical density and thickness against to Cu diffusion into Si substrate has been evaluated. Density of SiON films varied with deposition temperature using Plasma-Enhanced Chemical-Vapor-Deposition (PECVD) was ranged from 56% to 69% for bulk film. Cu diffusion increased with decreasing the film density, resulting in 3.5 × 1010 cm...
Through-silicon via (TSV) module-process based on wafer-on-wafer (WOW) stacking has been developed. Stacking wafers were thinned down to 20 μm, and TSVs with a diameter of 30 μm were fabricated to connect inter-wafers without electrical failure in chain TSV interconnects. The TSVs were constructed with the damascene technique. Multi-wafer stacking was realized by planarizing TSV-heads with a diamond...
High performance 45-nm Node and its 3D integration employed aggressively thinned down to 7-μm of 300-mm wafer for the Wafer-on-a-Wafer (WOW) application has been succeeded for the first time. The impact of ultra thin wafer on strained transistors and Cu/low-k multilevel interconnects is described. Properties examined include Kelvin and stack chain resistances of Cu interconnects as well as Ion-Ioff,...
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