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A technique is presented which allows an FPGA-based reconfigurable system-on-chip to automatically and dynamically load hardware peripheral controllers and software device drivers depending on the system's automated identification of peripheral boards which are connected to the FPGA. The technique loads peripheral detection modules into peripheral controller slots at system startup, and after these...
In this paper, the authors present a reconfigurable cluster-on-chip architecture and supporting parallel programming software library based on the well-known message passing interface (MPI) standard. The intent is to allow designers to program multi-core reconfigurable systems on chip using the same or similar methodologies that yielded tremendous productivity improvements in the workstation and HPC...
The post integration performance of cipher cores to a reconfigurable system-on-chip is a relatively unexplored area. There is also little work done on a stream aware cipher core. This paper presents an architecture that allows a cipher core to operate on multiple cipher streams without context switching. The integration of this architecture using fast simplex links to the microblaze soft-processor...
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