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With newer technology nodes, circuit/device/process codesign is essential to realize the advantages of scaling. Leveraging co-design approach based on a well-established manufacturing flow, a cost effective 28 nm 4G SOC technology has been crafted. This 28 nm design strategy uses two sets of design rules and 7 different Vt cells with optimal power gating to achieve a 2.4× increase in gate density,...
We observed Single Bit Read Disturb failure in SRAM blocks with embedded Flash process. Such failures are not observed in pure logic process because pure logic process does not require additional thermal budget. In embedded Flash process, static Noise Margin (SNM) and leakage current degrades, causing more Single Bit Failure (SBF) at high VCC and/or high temperature. We optimized SRAM bitcell's transistor...
Nano Beam Diffraction has been used to analyze the local strain distribution in MOS transistors. The influence of wafer process on the channel strain has been systematically analyzed in this paper. The source/drain implantation can cause a little strain loss but the silicidation step is the key process in which dramatic strain loss has been found.
High speed array architecture and cell optimization in the Uniform Channel Program and Erase (UCPE) floating gate 2 transistor (2T)-embedded flash cell (eFlash) are investigated. It is important to optimize select gate (SG) channel length from 2T-eFlash test array when CG flash device width/length and SG length are pre-determined by other constraints. SG-punch through (PT) driven Gate Disturb (GD)...
A programming disturb mechanism in the uniform channel program and erase (UCPE) eFlash 2TC (two transistor cell) is investigated. High GIDL current from the SG (selected gate) on the selected row and unselected columns introduce additional gate disturbs in a high density eFlash product. It is observed that the 1TC eFlash without an SG configuration did not show the same mechanism. When the SG bias...
Soft failure in static random access memory (SRAM), where there are several mechanisms related to it, is a kind of major obstruction to improve the yield. Transmission electron microscopy (TEM) is a powerful failure analysis tool, which has a high spatial resolution and is widely used in IC failure analysis with the shrinkage of integrated circuit to a nano-level transistor. Planar-view TEM techniques...
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