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In this paper, we propose an efficient 256×256 bit modular multiplier based on Montgomery reduction algorithm. The 256 × 256 bit modular multiplier is required in elliptic curve and pairing based cryptographic protocols to achieve 128 bit security level. The in-built features of modern FPGA are efficiently utilized. Two time consuming components (1) 512-bit addition (2) 256 × 256 bit multiplier are...
One of decisive feature in computer system design is the assessment of instruction pipeline. To design it carefully with minimum complexity to achieve enhanced performance and optimum result could be a powerful method. In order to achieve pipeline throughput close to ideal, the penalties of different hazards must be reduced. Branches are also one of those decisive substances that degrade the efficiency...
In-network aggregation, an important scheme for wireless sensor network, could save energy and bandwidth of the networks. But the unreliability of wireless links will weaken the performance of in-network aggregation deeply. In this paper, a novel in-network aggregation strategy using multi-nodes cooperation is studied. The key idea of the proposed strategy is that multi nodes aggregate data simultaneously...
Meeting the future requirements of higher bandwidth while providing ever more complex functions, future network processors will require a number of methods of improving processing performance. One such method will involve deeper processor pipelines to obtain higher operating frequencies. Mitigation of the penalty costs associated with deeper pipelines have achieved by implementing prediction schemes,...
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