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The technology uses TCP / IP as the basic means of communication, adding a custom data communication protocol, through the integration of distributed storage scheduling ideas, multiple FPGA development board simulation into a large number of storage devices, through the unified mapping of the target data protocol Processing, to achieve data security, stable and reliable cloud storage, and because...
Heterogeneous architectures face challenges regarding transparent acceleration as well as the allocation of resources to cores and accelerators. The “Transformer”, a run-time reprogrammable, heterogeneous architecture consisting of cores and reconfigurable logic with support for coarse-grained acceleration of the dynamic, unpredictable workloads present in mobile and cloud computing environments,...
In recent years, tail biting convolutional codes have been applied to the modern wireless communication standards, such as LTE and WiMAX. In this paper, the decoder for tail biting convolutional code with rate 1/2 and constraint length 7 is designed and implemented. Based on the circular property and the convergence rule of tail biting convolutional codes, we design the decoder using the Viterbi algorithm...
In the occasion of real-time requirements and harsh electromagnetic environments, currently adaptive filtering algorithm is most based on the DSP chip, using of Assembly Language and high-level language programming procedures, and the speed of processing and the performance of noise immunity are not match the requirement. LMS adaptive filter is a widely used digital signal processing algorithms. Due...
Ad Hoc network has the characteristics of self-organization and dynamic topology, so it can use polling strategy for data collection. In this paper, the data link layer of the Ad Hoc network data acquisition system has been carried out the detailed analysis and study, through the use of polling policy in the access network node to solve the problem of competition for resources and allocation mechanism...
This paper studies and designs of a car automatic driving control system, the system is a dual-core FFT processor based on the pipeline structure CORDIC algorithm design is based on the voice signal spectrum analysis, and through the to extract MFCC voice characteristics Template Library instruction data in comparison, thereby generating a control signal, and ultimately by the FPGA control the wireless...
This paper combined the coded excitation with the technique of ophthalmic high-frequency ultrasonic imaging, and proposed a new high-velocity data detection and signal processing method. 16-bit Golay complementary sequences were produced by FPGA, which excited the probe to produce ultrasonic waves. Data detection circuit achieved the digitalized of the 15 MHz high-frequency ultrasonic echo signals...
HDB3 (High Density Bipolar)is an improved bipolar RZ code, based on the AMI. HDB3 has no DC component, less low-frequency components, the number of attached zeroes is no more than 3. All of the three advantages are beneficial to signal timing recovery. In this paper, by using modern EDA technology, and assistance of FPGA devices and the VHDL, we have designed and realized HDB3 encoder, which has overcame...
Along with the rapid application of large-scale integrated circuit, computer system is growing by geometric series, the boundary between hardware and software has blurred. FPGA, a novel technology arisen in recent years has been challenged with the traditional hardware design, because the original method and mode cannot satisfy modern hardware system design. In this paper, we implement the complex...
This paper presents about the design and fabrication of a cost effective and portable system for real time monitoring and data analysis of cell cultivation applications based on CMOS sensor and microfluidic technology. The digital CMOS sensor has 2-Mpixel resolution and output digital data that is designed and fabricated on the 0.18um CMOS image process. The Chip has integrated with low noise 2 shared...
In order to achieve balanced flash memory writing in solid-state disks and extend their service life, dynamic mapping of logic sectors and actual physical sectors is established between the host device and the flash memory; A circular erasing algorithm is used to clean up dirty sectors produced in the sectors dynamic mapping process, and release invalid storage spaces effectively. The result of FPGA...
Onboard Reconfigurable Processing Platform (ORPP), which mainly consists of reconfigurable devices (FPGAs) and auxiliary co-processors such as DSPs, is dedicated to in-situ real-time computing for various space missions. Harsh ionizing radiation effects have been observed during flight thus make it crucial to design fault tolerance in ORPPs. Transient available refers to ORPP can mask transient faults...
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