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This brief presents a two-dimensional (2-D) Vernier time-to-digital converter (TDC) which uses two 3-stage gated ring oscillators (GROs) in the $X/Y$ Vernier branches. The already small Vernier quantization noise (∼10.6 ps) is improved by the first-order noise shaping of the GRO. Moreover, since all the delay differences between the $X$ and $Y$ phases can be used (rather than only the diagonal line...
We present a digital-to-time converter (DTC)-assisted fractional-N wide-bandwidth all-digital PLL (ADPLL). It employs a MASH ΔΣ time-to-digital converter (TDC) to achieve low in-band phase noise, and a wide-tuning range digitally-controlled oscillator (DCO). Fabricated in 40nm CMOS, the ADPLL consumes 10.7 mW while outputting 1.73 to 3.38 GHz (after a ÷2 division) and achieves better than −109 dBc/Hz...
We use a 2-dimensional (2-D) Vernier gated-ring-oscillator (GRO) time-to-digital-converter (TDC) in a cascade structure (MASH), so that a larger raw quantization step can be allowed without sacrificing the final resolution performance. The 2-D approach effectively reduces the latency time under a large input, while the MASH structure provides a 2nd-order noise shaping that produces a lower in-band...
We develop a novel traffic scheduling algorithm based on a master-slave linecard (LC) configuration to improve the energy-efficiency of hybrid fiber-coaxial (HFC) networks. The algorithm forwards packets to the master or slave LC adaptively according to the traffic load, and toggles the LCs between working and sleeping modes for energy-saving. To optimize the algorithm's key parameters, we model the...
The proposed time-to-digital converter (TDC) arranges two Vernier gated-ring-oscillator (GRO) branches in a 2-dimension (2-D) fashion. All delay differences between X phases and Y phases can be used, rather than only the diagonal line. The large latency time inherited from Vernier structure is therefore dramatically reduced. The TDC is implemented in a 90nm CMOS process and consumes 1.8mA from 1.2V...
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