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There is a desire to move current state-of-the-art niobium Josephson IC fabrication processes (/spl sim/3 /spl mu/m) to smaller sub-micron linewidths in order to realize a decrease in gate size and increase in both speed and packing density. However, cost and time dictates that a way be found to reuse the existing RSFQ gate/cell development that has been done at the 3-/spl mu/m level. Cell retargeting...
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