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This paper proposes methods to drastically reduce the expensive analog fault simulation currently used to create cell-aware fault models. By exploiting low-power properties of common CMOS designs, most defects in the transistor-level netlist containing parasitics can be represented by just two canonical fault classes. Via simple circuit analysis, we show that faulty behaviors are completely predictable...
This paper presents a power convertor design of a 60kW three-phase asymmetry half-bridge power convertor for switched reluctance machines (SRM). With established topology, voltage overshoot is sufficiently analyzed theoretically. To minimize voltage overshoot, this paper optimized the structure of main circuits, snubber capacitors and drive circuits. When dealing with main circuits structure, a low...
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