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The performance and robustness to PVT variations has been measured of an improved Self Synchronous FPGA (SSFPGA) designed in 65 nm CMOS which achieves 2.97 GHz throughput at 1.2V. The proposed SSFPGA employs a 38×38 array of 4-input, 3-stage Self Synchronous Configurable Logic Blocks, with the introduction of a new dual tree-divider 4 input LUT to achieve a 4.5× throughput improvement...
The reliable operation against PVT (process, voltage, and temperature) variation and aging effects has been measured of a Gate-Level Pipelined Self Synchronous FPGA (SSFPGA) design in 65nm CMOS. The SSFPGA employs a 38×38 array of 4-input, 3-stage Self Synchronous Configurable Logic blocks. Throughput has been measured at 2.97GHz at 1.2V, with correct operation from 750mV to 1.6V at 25°C. The operation...
A design environment for stripe-shaped PMELA TFTs on glass has been developed and successfully tested. Cell library including standard cells, logic synthesis database, place and route rule, layout parasitic extraction rule and transistor models are developed. Measurement results show that the digital circuits designed in this environment work correctly. They also show that the simulation environment...
In this paper, we have developed a design environment for a stripe-shaped PMELA process and have designed digital circuits such as a serial-to-parallel converter and a PRBS generator as examples of digital VLSI circuits. The designed circuits and standard cells are fabricated in bulk CMOS process and are verified their operations. The whole circuits are fabricated in PMELA 0.5 mum CMOS technology...
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