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This paper presents design of an all-digital fully-integrated 5th-order Gaussian pulse generator (PG) for full band (3.1GHz-10.6GHz) impulse radio ultra wideband (IR-UWB) transceiver SoC. The design is implemented in a foundry 0.18μm CMOS process. New FCC effective isotropic radiated power (EIRP) aware design technique is used to optimize the PG. Measurement shows peak pulse amplitude of 533mV at...
This paper reports a single-chip full-band 3.1 10.6GHz ESD UWB LNA featuring cascode shunt-series feedback topology and very robust whole-chip ESD protection. Careful ESD+LNA co-design was excised to achieve full-chip circuit optimization with high ESD protection. This design is implemented in a foundry 0.18μm RFCMOS process. Measurement shows the highest reported ESD protection of 8.25kV, a peak...
Adequate ESD protection is a new design challenge for HV electronics. This paper presents design, failure analysis and optimization of a HVggLDMOS ESD protection structure in a HV BCD process. Theoretical analysis involving Kirk effect and mixed-mode ESD simulation-design technique were used to analyze experimental results and to optimize the HV ESD protection structure.
We report design optimization of new low-triggering dual-directional SCR (LTdSCR) ESD protection structures in BiCMOS. Design optimization techniques to adjust ESD triggering voltage (Vt1), as well as its impacts on ESD holding voltage (Vh) and ESD protection capability, are discussed. Measurements show very low and adjustable Vt1, low leakage (Ileak), low noise figure (NF), low ESD-induced parasitic...
This paper reviews key factors to practical ESD protection design for RF and analog/mixed-signal (AMS) ICs, including general challenges emerging, ESD-RFIC interactions, RF ESD design optimization and prediction, RF ESD design characterization, ESD-RFIC co-design technique, etc. Practical design examples are discussed. It means to provide a systematic and practical design flow for whole-chip ESD protection...
This paper reviews advances in new 3D electro-thermal modeling technique for ESD (electrostatic discharge) protection structures. New 3D ESD device modeling is critical to full-chip ESD protection circuit design synthesis, verification, optimization and prediction, especially for IC designs in sub 100 nm CMOS technologies.
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