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In this paper, we present a high performance planar 20nm CMOS bulk technology for low power mobile (LPM) computing applications featuring an advanced high-k metal gate (HKMG) process, strain engineering, 64nm metal pitch & ULK dielectrics. Compared with 28nm low power technology, it offers 0.55X density scaling and enables significant frequency improvement at lower standby power. Device drive...
The application of 3D Network on Chip (NoC) provides an effective way for tackling the performance bottleneck for high-performance Systems on Chips (SoCs). How to design an efficient 3D Network on Chip which is satisfied with the communication requirement of 3D system and simultaneously enables significant performance enhancements has encouraged a lot of attention. In this paper, we focus on the automatic...
Networks on chip (NoC), a new packet-based design method, with a new dependable no deadlock (DND) back-tracking routing algorithm are proposed to implement artificial neural network (ANN). This system is simulated by NIRGAM NoC simulator to get system performance. Experimental results show that this proposed system has higher connection-per-second (CPS), lower communication load than the exiting other...
In modern superscalar processor, branch misprediction penalty becomes a critical factor in overall processor performance. Previous researches proposed dual (or multi) path execution methods attempt to reduce the misprediction penalty, but these methods are quite complex and high power consumption. Most of the reasons are due to simultaneously fetching and executing instructions from multiple. In this...
NAND flash memories are used in digital still cameras, cellular phones, MP3 players and various memory cards. As seen in the growing needs for applications such as solid-state drives and video camcoders, the market demands for larger-capacity storage has continuously increased and NAND flash memories are enabling a wide range of new applications. In such situations, to achieve larger capacity at low...
Recently, networks-on-chips (NoCs) have a great development and have been proposed as a promising solution to complex on-chip communication problems. One of the problems is an application of artificial neural networks (ANNs). In this paper, we propose NoCs for the ANNs. NoCs is designed to implement a BP-ANNs (back-propagation) and evaluated by network-on-chips. Experimental results show that for...
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