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A W-band power amplifier in 65-nm CMOS technology is presented in this paper. This PA is a 3-stage common source design using thin film microstrip lines to realize the matching network. Choosing high-pass topology for the inter-stage matching network and low-pass matching for the input and output to compensate device frequency response, we achieve a wide band and high output power PA. From the measurement...
The linearity and power added efficiency (PAE) of the power amplifier (PA) are improved by reversed body bias (RBB) using 0.18-µm CMOS technology and the bias dependence of the circuit performances is investigated. Negative bias to the bulk and forward bias to the deep n-well of the MOSFET devices are used to reduce the effects of the parasitic diodes and change the threshold voltage (Vth), leading...
This paper presents a 50–70 GHz wideband I/Q modulator with improved sideband suppression. The sideband suppression improvement results from the on-chip HPF/LPF based broadband quadrature power splitter. The I/Q modulator exhibits conversion gain of −6 to −2 dB from 50–70 GHz. The LO-RF isolation is better than 36 dB. The sideband suppression is better than 19 dBc from 50 to 75 GHz.
A fully integrated 24-GHz 22-dBm power amplifier was designed and fabricated in 0.18-µm CMOS technology. Optimized device size selection and resonance matching techniques are adopted in this single stage power amplifier design. High pass matching circuit is used to reduce output losses and maintain gain flatness. The measurement results shows a 22 dBm of saturation power and 20 dBm of output power...
An X-band high efficiency power amplifier with the highest PAE is presented in this letter. The single-stage power amplifier is implemented in TSMC standard bulk 0.18-μm 1P6M CMOS technology. In order to obtain wide bandwidth at PAE and output power, broadband output and input matching network are adopted in the design. From the measurements, the power amplifier obtained the best PAE of 25.8% and...
This paper presents a 40-80-GHz SPDT switch fabricated in mHEMT process. The SPDT switch accomplished insertion loss lower than 2.4 dB and isolation better than 23 dB. Via holes were shared to compact the layout and the chip size of 1 x 1 mm2 is obtained. Table 1 summarizes recently reported performance of SPDT switches in GaAs HEMT process.
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