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This paper presented a method to examine the electrical characteristics of sidewall insulation layer of through silicon via (TSV), including breakdown voltage and sidewall capacitance. Blind via samples were fabricated for the experiment using deep reactive ion etching. 2μm SiO2 insulation layer was deposited using PECVD (Plasma enhanced chemical vapor deposition). Ti/W/Cu adhesive/barrier/seed layer...
In this paper, we present our recent advances in streamlining via-last TSV process flow. Parylene deposition, which is of excellent conformability to the substrate landscape, was introduced into TSV blind via filling process to realize uniform sidewall protection. Simulation was made to analyze the impacts of parylene sidewall on the electric field distribution inside a blind via with high aspect...
This paper focused on the process of forming sidewall insulation of through silicon via (TSV) which was a challenging bottleneck in 3D integration technologies. In traditional way, etching silicon oxide on via bottom would reduce the thickness of sidewall insulation layer inevitably, which might lead to the failure of TSV sidewall insulation and electrical interconnection characteristic. In this paper,...
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