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We demonstrated a high-k/metal gate-last SiGe-SOI CMOSFET process with optimized strain technology for high performance concerns. The impact of SOI thickness and strain from Ge, CESL, and high-k material/metal-gate are inspected. An appropriate post treatment is proposed to improve quality of stack Hf-based dielectric. We achieved a high manufacturability 28nm SiGe-SOI channel Hf-based high-k/TiN-based...
A ??hybrid?? high-k/metal gate (HK/MG) integration scheme is proposed in this paper to accomplish HP (high performance) 28 nm CMOSFETs by integrating gate-first/gate-last (GF/GL) techniques for N/PFET, respectively. For NFET, remarkable mobility (95% of n+poly/SiON@1MV/cm) and low VTH (0.25 V) was achieved through optimized HfO2 high-k, TiN metal and LaOx capping layer processes. For PFET, an extra...
Low power designs create new challenges in design implementation, verification and testing. DFT practice that overlooks test power may result in yield loss/overkill during manufacturing test. This paper addresses the practical problems often encountered during DFT implementation and manufacturing test for complex low power designs.
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