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The P̅ANDA detector at the future FAIR facility in Darmstadt, Germany will operate with a very high anti-proton interaction rate of up to 2 × 107/s in a free streaming mode without hardware triggers. Several hundreds of GB/s of data have to be read out. Sophisticated event filtering mechanisms based on tracking, calorimetry and particle identification are required in order to reject background events...
With increasing design complexity System on Chip (SoC) verification is becoming a more and more important and challenging aspect of the overall development process. The Universal Verification Methodology (UVM) is thereby a common solution to this problem; although it still keeps some problems unsolved. In this panel leading experts from industry (both users and vendors) and academy will discuss the...
This paper presents a post-silicon debug methodology that provides a means to rewind, or backspace, a chip from a known crash state using a combination of on-chip real-time data collection and off-chip formal analysis methods. A complete debug flow is presented that considers practical considerations such as area, on-chip non-determinism and signal propagation delay. This flow, along with a low-overhead...
This paper presents TAB-BackSpace, our novel scheme to provide the effect of an unlimited-length trace buffer with no on-chip overhead beyond the existing debug logic. We present the theoretical foundation of our work, simulation studies on how we reduce the possibility of computing an erroneous trace, and results from the bring-up lab on real silicon of an IBM POWER7 processor, where TAB-BackSpace...
This paper describes a new course on mixed-signal IC test engineering, jointly established by the Department of Electrical and Computer Engineering (ECE) of The Ohio State University and Texas Instruments. The course is motivated by the lack of qualified test engineers in industry and the absence of this education at the collegiate level. The course objective is to help student obtain the fundamental...
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