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The demand for high-quality and high-speed imaging has increased. Column-parallel ≥14b A/D conversion is one of the major approaches to meet these requirements in CMOS image sensors (CIS). Oversampling ADCs such as incremental delta-sigma (I-ΔΣ) ADCs are the solution for a high-resolution ADC having tolerance of analog component errors. Oversampling reduces input temporal noise as well as the quantization...
An all-digital 90deg phase-shift DLL is proposed for 1.6 Gbps DDR interface by using a loop-embedded DCC and a binary phase detector with the lock range extended to 0~4pi radians. The DCC has a small delay and the fixed rising-edge property for loop-embedding. The chip fabricated with a 0.13 um CMOS process gives the DLL data rate of 667 Mbps~1.6 Gbps and the output duty cycle of 47.8%~49% for the...
A versatile I/O buffer is proposed to interface DDR/DDR2/GDDR3 memory types. A new robust impedance calibration scheme which fills the role of off-chip driver (OCD) and on-die terminator (ODT) for improving signal integrity is introduced. The proposed calibration scheme minimizes quantization error and maintains 30~300Omega impedance within 3% variations
A slew rate controlled output driver adopting delay compensation method is implemented using 0.18 µm CMOS process for storage device interface. Phase-Locked Loop is used to generate compensation current and constant delay time. Compensation current reduces the slew rate variation over process, voltage and temperature variation in output driver. To generate constant delay time, the replica of VCO in...
A method of utilizing impedance control techniques using thermometer code and internal current source to create high performance USB2.0 transceiver is described in this paper. Since digital signals are the only inputs to these new impedance control circuits, on-chip dc power dissipation can be reduced, the circuit can be made more robust, and the impedance of the circuit can be adjusted by manipulating...
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