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Meeting performance targets of 22 nm Si- CMOS and beyond, as per 2006 ITRS update, will require innovation at all levels of CMOS development, including new channel materials, device design, integration, circuit design, and system architecture. In new channel materials, some of the options under consideration include (a) local and global strain, (b) Si surface orientation, and (c) non-Si materials...
In this work, we present the results of physical and electrical characterization of Ti-based high-k gate dielectrics on Ge substrates. To improve the electrical properties, nitrogen engineering has been employed to convert the lossy GeO2 interfacial layer to its oxynitride, and thus forming a TiO2/GeOxN3/Ge stacked-gate structure with improved interfacial and electrical properties. Charge trapping,...
Internal photoemission and magnetic resonance studies have been performed to investigate the charge trapping kinetics and chemical nature of defects present in ultrathin high-k dielectric films deposited on p-Ge (100) substrate. Both the band and defect-related electron states were characterized through EPR, IPE, C-V and I-V measurements under UV-illumination. The interface trap spectrum in Ge/high-k...
Ultra thin high-k ZrO2 films (14 nm) have been deposited on germanium at a low temperature (~150degC) using microwave plasma enhanced chemical vapor deposition (PECVD) technique. Several samples were NO-plasma nitrided before deposition of the high-k films to minimize the surface roughness and interdiffusion of germanium. Using Capacitance-time (C-t) technique the value of bulk generation lifetime...
Process simulation for germanium MOSFETs (Ge-MOSFETs) has been performed in 2D SILVACO virtual wafer fabrication (VWF) suite towards the technology CAD for Ge-CMOS process development. Material parameters and mobility models for Germanium were incorporated in simulation via C-interpreter function. We also report on the device design issues along with the DC and RF characterization of the bulk Ge-MOSFETs,...
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