The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Meeting performance targets of 22 nm Si- CMOS and beyond, as per 2006 ITRS update, will require innovation at all levels of CMOS development, including new channel materials, device design, integration, circuit design, and system architecture. In new channel materials, some of the options under consideration include (a) local and global strain, (b) Si surface orientation, and (c) non-Si materials...
As scaling laws become less effective in boosting performance for CMOS devices for 90 nm and below, substrate- and process-induced strain engineering are playing an ever increasing role in performance enhancement. Strained-Si MOSFETs are also attractive for high speed and low power applications (Maiti et al., 2007). Ultra thin SiO2 gate dielectrics, of less than 1.5 nm in thickness, are needed for...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.