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This paper proposes a merged first and second stage for pipelined ADC. It merges the first MDAC and second MDAC by using opamp and capacitor sharing technique to reduce power. For low supply advanced CMOS technology, the range-scaling technique is used to reduce output range in this stage, so the single-stage opamp can be used with low supply voltage to reduce power furthermore. The SHA-less technique...
A nanopower subthreshold bandgap reference with 30ppm/°C from −30°C to 150°C has been implemented in 0.18µm CMOS. This design is based on weighted ΔVGS and is free of resistors. The major advantage of this design is that with nanopower consumption, the temperature range is extremely wide. To achieve high performance of subthreshold bandgap operating in high temperature (above 80°C), a leakage current...
A wide tuning range LC VCO with auto amplitude control is designed in 0.13-μm CMOS. Phase noise optimized design for the wide tuning range VCO is discussed and a PVT insensitive digitally reconfigurable auto amplitude calibration (AAC) circuit is used to stabilize the phase noise in the whole wide band. The proposed AAC circuit with a code estimated FSM provides faster operation to get the optimum...
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