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The latest multiple-input multiple-output (MIMO) wireless systems have adopted iterative detection and decoding (IDD) to reduce the signal-to-noise ratio (SNR) required fora reliable transmission. An IDD system consists of a soft-in soft-out (SISO) detector to cancel interference, and a SISO forward-error correction (FEC) decoder to remove errors. The two blocks exchange soft information to improve...
We present a low-power high-speed ultra-wideband (UWB) pulse radio transmission test platform. The transmitter circuit is fabricated on the Peregrine semiconductors 0.5 micron silicon-on-sapphire (SOS) CMOS process and packaged in a DIP16 package. 12.5 Mbps data rate of wireless transmission is achieved. The power consumption of the transmitter is 10 mW when the pulse rate is 90 MHz. The core circuit...
We present a low-power pulse-based amplifier and data conversion circuit for recording bio-potentials. The circuit is designed for data reduction in neurophysiological sensor and communication systems. A low-power low-noise AC amplifier with an asynchronous delta A/D converter is implemented. The asynchronous delta modulation has the advantage of data reduction, clock-less and no quantization noise...
A low-power tunable transmitter for ultra-wide band (UWB) radio was designed and fabricated. The design is based on a ring oscillator VCO, to produce short pulses. Both the pulse duration and frequency is controllable by two voltage biases. The transmitter can be used in both pulse-amplitude modulation (PAM) and pulse-position modulation (PPM). The circuit was fabricated on a 0.5mum silicon-on-sapphire...
We introduce a new method to measure the crosstalk power penalty in an arrayed environment by using an on-chip pseudorandom-bit-sequence generator to drive the aggressors. The proposed method is implemented in a three-channel 3.125-Gbit/s/ ch parallel receiver. Experimental results are presented including measurements of bit-error rate and crosstalk power penalty for 2.5and 3.125-Gbit/s operations...
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