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Poly-Si thin-film transistor (TFT) is the key building element for high-density 3D NAND Flash memory. Random grain boundary (GB) location and interface traps (Dit) density have been shown as the major root cause of variability [1]. However, with CNL pinned at midgap our previous model cannot adequately address experimental results - especially the cause of very low Vt TFT devices. In this work we...
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