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Simulation speed is a key issue in virtual prototyping of Multi-Processors System on Chip (MPSoCs). SystemC TLM2.0 (Transaction Level Modeling) is now commonly used to accelerate the simulation. However, the standard SystemC simulation engine uses a centralized scheduler that is clearly a bottleneck to parallelize the simulation of architectures containing hundreds of processor cores, and involving...
This paper presents a method for designing SystemC-compliant Instruction Set Simulators (ISS) that address three of the major problems system designers are faced with when modeling MP-SoCs architectures: the multiple levels of abstraction of the simulation models supporting the design space exploration, the simulation speed, and the debug of the multithreaded embedded application. First, this paper...
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