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In this paper, we discuss the scalable NLDMOS design in a 0.18μm HV-CMOS technology. The design impacts in quasi-saturation are compared between the 25V and 50V NLDMOS to demonstrate the implications in output and fT characteristics. The STI depth sensitivity in DC, ac and HCI characteristics is investigated. The results prove a very robust design, featuring <10% Idlin shift over 10 year lifetime...
In this paper, we discuss a method to extrapolate intrinsic and extrinsic Ron components for a JFET. The results provide the guideline to lower Ron, hence to achieve competitive “Ron vs. pinch off (Voff)” benchmark. The optimization impacts on channel length scaling and process variation are discussed. Besides, an improved RESURF condition is achieved using one of the experimental conditions. The...
In this paper, we present a cost-effective JFET integrated in 0.18μm RFCMOS process. The design is highly compatible with standard CMOS process, therefore can be easily scaled and implemented in advanced technology nodes. The design impact on Ron and Voff is further discussed, providing the insights and guidelines for JFET optimization. Besides the superior flicker noise (1/f noise) characteristics,...
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