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With the growing number of smartphone users, peer-to-peer ad hoc data forwarding is expected to occur more often. The forwarding performance improves when knowledge regarding the expected topology and the social context information of the networks. In this paper, we introduce a new metric for data forwarding based on social context information, in which node's social context information is used to...
Low power consumption and reliability become vital in Network-on-Chip (NoC) designs with growth of integrated circuits complexity. In this paper, we propose a novel architecture with buffer-shared router structure to reduce buffer redundancy. Accordingly, the proposed defect-tolerant routing algorithm can effectively associate with improved intra-router architecture to improve reliability of NoCs...
As technology advances, the voltage (IR) drop in the power/ground (P/G) network becomes a serious problem in modern IC design. The P/G network co-design with floorplan can improve the power design quality. Different with traditional approaches which analyze P/G network during the floorplanning iterations, in this paper, an efficient pattern selection method is used to provide gradient information...
In current VLSI design, routing congestion becomes a critical issue with deep submicron design technology. In order to avoid the rip-up and reroute which is a time-consuming process after the placement stage, in this paper, we proposed a new two-stage floorplanning approach for congestion optimization. In our approach we use the method of probability-estimation which uses the extended bounding box...
Field programmable gate arrays (FPGAs) are becoming increasingly important implementation platforms for digital circuits. This paper presents a method for symmetrical FPGA placement based on ant colony optimization (ACO). Also, we take the routing congestion into consideration by introducing a congestion factor in our algorithm. Experimental results show that compared with the state-of-the-art FPGA...
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