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This paper introduces a 51.2Gops, 1.0GB/s-DMA single-chip multiprocessor integrating quadruple cores and proposes a power integrity analysis. Our multiprocessor is designed to decode MP@HL streams without any dedicated circuits. To achieve such high performance, data throughput as well as processing capability is important, requiring a large number of high speed I/Os. However, this makes for a high...
A 51.2-GOPS chip multi-processor integrates four 8-way VLIW embedded processors with 1.0 GB/s local-bus direct memory access. This IC completes MPEG2 MP@HL video-stream decoding at 68% of its processor capability without dedicated hardware. The 11.9 mm /spl times/ 10.3 mm chip is fabricated in a 90 nm 9M CMOS process and consumes 5 W at 533 MHz.
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