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This paper proposes a flexible dual-mode soft-output multiple-input multiple-output (MIMO) detector to support open-loop and closed-loop in Chinese enhanced ultra high throughput (EUHT) wireless local area network (LAN) standard. The proposed detector uses minimum mean square error (MMSE) sorted QR decomposition (MMSE-SQRD) to produce channel preprocessing result, which is realized by a modified systolic...
High Efficiency Video Coding (HEVC) is new video coding standard beyond H.264/AVC. In this paper, an area and throughput efficient 2-D IDCT/IDST VLSI architecture for HEVC standard is presented. Adopting proposed data flow scheduling and shared constant multiplication structure, the architecture supports variable block size IDCT from 4×4 to 32×32 pixels as well as 4×4 pels IDST. Using 65nm technology,...
Real-time constraints pose a new challenge when performing real-time application mapping onto Network-On-Chip. To this problem, we first propose a new task graph description in this paper, to enable both computation mapping and communication scheduling. Based on the proposed graph, we then propose a contention and energy aware mapping algorithm to eliminate the communication conflicts and reduce energy...
Quadratic permutation polynomial (QPP) interleaver is a contention-free interleaver which is suitable for parallel turbo decoder implementation. In this paper, a systematic recursive method to design configurable QPP interleaving multistage network is proposed based on the property of QPP. Due to the nature of recursion, the proposed network for 2n-level parallel turbo decoder can be used for any...
High throughput and high computation many core based on chip architecture is a development trend for high performance digital signal processing platform design. With frame and block data processing technology feature, the general linear memory architecture and on chip interconnection scheme may cause performance bottleneck for the application. In this paper work, we propose a 64-core array on chip...
In order to solve the transponder collision problem in a RFID system, this paper proposes a hybrid algorithm which combines strengths of existing high-performance algorithms while avoiding their major drawbacks. Experiments show this hybrid algorithm uses fewer time slots and less total communication time compared to adaptive slot-count algorithm based on ALOHA as well as enhanced anti-collision algorithm...
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