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In highly reliable CMOS integrated circuits, parasitic parameters have dramatic impacts on SER(soft error rate) estimation and affect the design decision. We proposed a circuit level SER characterization framework(ASSET-SPI) to evaluate the impacts by conducting statistical fault injection experiments automatically on the circuit spice netlist containing parasitic parameters. Experiments on ISCAS...
A customized design flow for ultra-low power cell library and an 8-bit ultra-low power microprocessor for wireless sensor network application are presented in this paper. According to the logic pre-synthesis results of the 8-bit microprocessor HDL code, frequently used standard cells are collected to develop a customized sub-threshold cell library through size and structure modifications. The ultimate...
As a major sequential logic element, D flip-flop is an indispensible cell in logic cell library. In this paper, we proposed two improved sub-threshold D flip-flop circuits (mTGMS and emC2MOS D flip-flop) after conducting robustness analysis of several typical flip-flop circuits. Using SMIC 0.18um CMOS technology, the simulation results show that the minimum work voltage of our proposed mTGMS and emC...
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