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In order to achieve high tolerance against process, voltage, and temperature variations in the ultralow voltage (ULV) circuits, in situ error detection and correction (EDAC) techniques were presented. However, circuits adding the capability of error detection incur large hardware overhead, especially in ULV due to larger delay variability. In this paper, we analyze the hardware overhead of error detection...
This paper presents a static-placement, dynamic-issue (SPDI) framework for the coarse-grained reconfigurable architecture (CGRA) in order to tackle the inefficiencies of the static-issue, static-placement (SISP) CGRA. This framework includes the compiler that statically places the operations and hardware design, a SPDI CGRA, that automatically schedule the operations. We stress on introducing the...
Coarse-Grained Reconfigurable Architectures (CGRA) are promising accelerators with high performance and power-efficiency. Most compilers map loop kernels of the compute-intensive applications onto CGRA through modified modulo scheduling algorithms. EPIMap converts the problem into finding a subgraph of time extend CGRA that matches modified data flow graph (DFG). Therefore, the number of nodes and...
In this paper, we will present a block cipher circuit design against Power Analysis. This design consists of usual masking and hiding method. For XOR, permutation and other linear layer, masking method of protection is used, but for S-box and other non-linear layer, hiding method is used in the reason that masking requires a lot of hardware consumption. We accomplished hardware implementation and...
Reconfigurable computing arrays facilitate the flexibility with high performance for regular and computation-intensive algorithms in multimedia processing. However, the efficiency of the irregular and control-intensive algorithms becomes the performance bottleneck of reconfigurable multimedia systems. In this paper, we propose the design and VLSI implementation of a novel memory efficient macroblock...
Time domain interleaved partitioning partial transmit sequence method (TD-IP-PTS) needs only one inverse fast Fourier transform (IFFT) to reduce peak-to-average power ratio (PAPR) of orthogonal frequency division multiplexing (OFDM) system. However, for one long OFDM symbol, it will need waiting time and many registers to implement the combination of phase factor in TD-IP-PTS. Therefore, the speed...
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