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The sensitivities of a Monte Carlo simulation tool (PRESTAGE) to variation of input parameters are studied. When calculating the single event upset cross-section induced by proton direct ionization, PRESTAGE calculation results significantly change with changes in the sensitive volume and passivation layer thicknesses. When calculating cross-sections induced by proton indirect ionizations, PRESTAGE...
FPGA has been used in many fields such as space, military, auto. It is the best choice of cipher protocol and artithmetic achievement. Its security has been a focus. In this paper, the authors design a Hardware Trojan of transmitting key information towards FPGA. It is important to realize the implement mechanism and raise the attention to IC security.
In this paper, we present an FPGA implementation of a low complexity affine projection (AP) adaptive filtering algorithm based on a novel low complexity recursive filtering technique and filter update that is incorporated in dichotomous coordinate descent iterations. This adaptive algorithm is simple for finite precision implementation, requires small chip resources, and exhibits numerical stability...
In this paper, we present an FPGA implementation of a Recursive Least Squares adaptive filtering algorithm based on dichotomous coordinate descent iterations. The algorithm is simple for finite precision implementation, requires small chip resources, and exhibits numerical stability. For arbitrary regressors (as in antenna array beamforming), the proposed implementation allows significant increase...
In this paper, we present an FPGA implementation of a dynamically regularized recursive least squares adaptive filtering algorithm based on dichotomous coordinate descent iterations. The algorithm is simple for finite precision implementation, requires small chip resources, and exhibits numerical stability. The proposed implementation allows significant increase in the weight update rate compared...
The recursive least squares (RLS) adaptive filtering problem is expressed in terms of auxiliary normal equations with respect to increments of the filter weights. By applying this approach to the exponentially weighted case, a new structure of the RLS algorithm is derived. For solving the auxiliary equations, dichotomous coordinate descent (DCD) iterations with no explicit division and multiplication...
A field-programmable gate array (FPGA) implementation of a new algorithm for multiuser detection (MUD) is presented in this paper. This FPGA design is based on the dichotomous coordinate descent (DCD) algorithm. The DCD algorithm allows the multiplication-free solution of the normal equations appearing in the MUD problem. This results in an area-efficient FPGA design that requires about 400 slices...
Parallel implementation of the dichotomous coordinate descent (DCD) algorithm is proposed and analyzed. The DCD algorithm allows multiplication-free solution of the normal equations. The computational load of the algorithm is mainly due to "successful" iterations, when an iV-length auxiliary vector is updated, N being the problem size. The parallel design exploits the fact that elements...
The FPGA design of an adaptive antenna array beamformer is presented. The complex-valued array weights are calculated using the MVDR algorithm whose implementation is based on dichotomous coordinate descent (DCD) iterations. The DCD algorithm allows the multiplication-free solution of the normal equations, resulting in an area-efficient FPGA design that requires approximately 400 slices for the DCD...
Based on FPGA, a digit-serial FIR filter is implemented. According to the digit-serial algorithm, the digit-serial FIR filter is composed of foundational function modules including the digit-serial adder, the digit-serial multiplier and the delay circuit. Compared with the traditional method, the digit-serial FIR filter based on FPGA exhibits the advantages of high response speed and low hardware...
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