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Transactional memory (TM) is a new shared resource synchronization mechanism which was proposed to ease the difficulty of parallel programming. Currently, most hardware transactional memory systems leverages the extended directory based cache coherence protocol to resolve transaction conflicts; seldom research has been conducted to extend a snoopy coherence based chip multi-processor with TM support...
In the era of multi-core processors, the challenge of designing a high efficient memory system is more severe than before. This paper focuses on the memory hierarchy design and implementation on a multiprocessor system. With the distributed shared memory (DSM) model, some techniques have been presented to improve the performance of traditional memory hierarchy and simplify the complexity of cache...
Supporting unbounded transactions and operating system (OS) are two notable challenges that need to be efficiently resolved by practically accepted hardware transaction memory (HTM) systems. Current proposals that heavily rely on traditional cache system to handle version management or conflict detection support poorly to resolve these two challenges. Traditional approach brings either unavoidable...
Recent years, it has been a hot research topic on providing efficient and unbounded transactional memory support through hybrid hardware and software approach. Yet, current proposed systems which buffer transactional data in traditional data cache have high overhead and design complexity. In this paper, we propose a new design approach to build hybrid transactional memory system. Our approach adds...
Transactional memory (TM) provides efficient, easy, deadlock-free parallel programming model for today's multicore-ubiquitous hardware platform. Implementation of TM needs to guarantee that the transaction is executed atomically and in isolation. Our paper proposes an efficient and unbounded hybrid-mode TM system with strong isolation guarantee, called HybridTCache. HybridTCache optimizes the common...
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