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Single input change (SIC) test sequences have been investigated in recent years because it is effective to more test fault types and test power reduction. In this paper, generation of sequential SIC (SSIC) test sequences based on deterministic built-in self-test (BIST) is proposed for decreasing the test power consumption and test application time with high test fault coverage. Furthermore, several...
A new single input change (SIC) test pattern generator (TPG), called multi two-bit twisted ring counters (MTB-TRC), is presented in this paper. Experimental results based on ISCAS'85 benchmark circuits show that the proposed MTB-TRC has the improved performance (power, fault coverage and test length), compared with the corresponding already known TPGs. Another advantage of the proposed MTB-TRC is...
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